Integrated circuits are used in many portable electronic products, such as cell phone, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc. Across virtually all applications, there continues to be demand for increasing functions and reducing the size of the devices. The intense demand is no more visible than in portable electronics that have become so ubiquitous.
In the manufacture of integrated circuit devices it is necessary to provide electrically conductive contacts and interconnect layers in order to connect electrically various parts of the device to each other and to external circuitry. Manufacturers of integrated circuit devices have appreciated that there is a need further to reduce the size of the devices, such as by reducing the size of the electrical contacts as well as the interconnect pitch, without reducing the reliability of the devices and keeping the surface planar so that subsequent interconnect layers can be formed.
Conventional methods of depositing metal contacts, such as by sputtering, have great difficulty in depositing enough material into the contact holes in order to form reliable electrical connections between the substrate silicon and the metal contact. In addition, the resulting topology is non-planar and can place severe constraints on the complexity of the interconnect layers. This method of manufacturing has the limitation that the contact hole must be wide enough and have the correct profile to allow a limited amount of metal to enter the contact hole to form the contact. The obtainable reduction in size of the contact hole is limited by the step coverage capability of conventional sputtering systems.
In addition, the metal line width has to be large enough to cover the contact by at least the possible misalignment of the pattern so that the contact is protected during etching of the metal to form the desired patterning of the interconnect layer. Furthermore, by making the contact hole large, any subsequent dielectric layer not only has to be capable of covering the non-planar surface resulting from previous interconnect layers but also has to cover the profile of the interconnect material when it goes down into a contact hole. This requires complex and involved techniques for planarizing the next dielectric layer, which must be used if further layers, in particular interconnect layers, are desired.
Thus a need still remains for an integrated circuit contact system to provide increasing density without sacrificing reliability, yield and high volume manufacturing processes. In view of the increasing demand for density of integrated circuits and particularly portable electronic products, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.